Optimize the ARM64 code path (the primary target for Nostr clients):
1. fe_mul_asm: Use LDP/STP (load/store pair) to load all 8 limbs in
4 instructions instead of 8 individual LDR. Row 0 in hand-tuned
ASM with MUL+UMULH+ADDS/ADC. Rows 1-3 in __int128 C (ARM64 gcc
generates optimal MUL+UMULH+ADDS/ADCS and MADD from this).
2. fe_normalize: Branchless on ARM64 using mask-based conditional
subtract (compiles to CSEL/AND on ARM64, avoiding branch
misprediction on mobile Cortex-A76+ SoCs). x86_64 keeps the
branching version since its branch predictor handles the >99.99%
non-taken case perfectly.
3. Document ARM64-specific instruction usage:
- MUL + UMULH: 64×64→128 product (1 cycle throughput on A76+)
- LDP/STP: load/store pair (2 regs per instruction)
- ADDS/ADCS: carry chain for accumulation
- MADD: fused multiply-add (generated by gcc from __int128)
These changes don't affect x86_64 correctness or performance
(verified: all keys pass, benchmark matches previous numbers).
The ARM64 improvements will be measurable when built with the
Android NDK for actual phone testing.
https://claude.ai/code/session_011KVZhDcV2G7idNWEBz12GY
Claude
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