perf: add x86_64 and ARM64 inline ASM for field multiply
Platform-specific inline assembly for fe_mul: x86_64: Uses MULQ instruction for 64x64->128 products. Row-based schoolbook with ADC carry chain. Reduction uses MULQ for hi[i]*C. Eliminates redundant register moves that __int128 compilation generates. ARM64: Uses MUL+UMULH instruction pairs for 64x64->128 products. First row in ASM with ADDS/ADC carry chain, remaining rows use __int128 (which ARM64 gcc compiles well). Reduction in __int128. fe_mul: 20.1ns → 17.2ns (14% faster on x86_64) gej_double: 242ns → 224ns (7.4% faster) verifyFast: 37.2µs → 36.5µs (27,397 ops/s) signXOnly: 19.2µs → 18.5µs (54,054 ops/s) https://claude.ai/code/session_011KVZhDcV2G7idNWEBz12GY
This commit is contained in:
Claude
@@ -8,6 +8,7 @@
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* the lazy reduction advantage of 5x52 on both JVM and native.
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*/
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#include "field.h"
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#include "field_asm.h"
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#include <string.h>
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#define FIELD_C 0x1000003D1ULL
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@@ -123,7 +124,10 @@ void reduce_wide(secp256k1_fe *r, const uint64_t w[8]) {
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}
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void fe_mul(secp256k1_fe *r, const secp256k1_fe *a, const secp256k1_fe *b) {
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#if HAVE_INT128
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#if FE_MUL_ASM
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fe_mul_asm(r, a, b);
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return;
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#elif HAVE_INT128
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/* Inline mul + reduce to avoid function call overhead and enable
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* the compiler to keep intermediates in registers. */
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uint64_t a0=a->d[0], a1=a->d[1], a2=a->d[2], a3=a->d[3];
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@@ -0,0 +1,320 @@
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/*
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* Copyright (c) 2025 Vitor Pamplona
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*
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* Platform-specific field multiply/square using inline assembly.
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*
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* ARM64: MUL + UMULH pairs for 64x64->128 products (2 instructions, 3 cycles each)
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* x86_64: MULQ for 64x64->128 products (1 instruction, 3 cycles each)
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*
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* The compiler's __int128 code is decent but not optimal:
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* - On x86_64: gcc generates MULQ correctly but adds unnecessary MOVs
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* - On ARM64: gcc sometimes uses UMULL (32-bit) instead of MUL+UMULH (64-bit)
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*
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* These hand-tuned versions keep intermediates in registers and avoid
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* redundant moves, saving ~2-3ns per fe_mul (~10% of verify).
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*/
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#ifndef SECP256K1_FIELD_ASM_H
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#define SECP256K1_FIELD_ASM_H
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#include "secp256k1_c.h"
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#define FIELD_C_ASM 0x1000003D1ULL
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#if SECP_X86_64 && defined(__GNUC__) && !defined(__clang_analyzer__)
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/*
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* x86_64 field multiply using MULQ instruction.
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* MULQ multiplies RAX by the operand, producing RDX:RAX (128-bit result).
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* We use a row-based approach: multiply each a[i] by all b[0..3],
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* accumulating into output registers.
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*/
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static inline void fe_mul_asm(secp256k1_fe *r, const secp256k1_fe *a, const secp256k1_fe *b) {
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uint64_t lo0, lo1, lo2, lo3, hi0, hi1, hi2, hi3;
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uint64_t a0 = a->d[0], a1 = a->d[1], a2 = a->d[2], a3 = a->d[3];
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/* Row 0: partial product a0 * b[0..3] */
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__asm__ __volatile__(
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"movq %[a0], %%rax\n\t"
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"mulq %[b0]\n\t" /* rdx:rax = a0*b0 */
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"movq %%rax, %[lo0]\n\t"
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"movq %%rdx, %%r8\n\t" /* r8 = carry */
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"movq %[a0], %%rax\n\t"
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"mulq %[b1]\n\t" /* rdx:rax = a0*b1 */
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"addq %%r8, %%rax\n\t" /* add carry */
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"adcq $0, %%rdx\n\t"
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"movq %%rax, %[lo1]\n\t"
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"movq %%rdx, %%r8\n\t"
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"movq %[a0], %%rax\n\t"
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"mulq %[b2]\n\t"
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"addq %%r8, %%rax\n\t"
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"adcq $0, %%rdx\n\t"
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"movq %%rax, %[lo2]\n\t"
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"movq %%rdx, %%r8\n\t"
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"movq %[a0], %%rax\n\t"
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"mulq %[b3]\n\t"
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"addq %%r8, %%rax\n\t"
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"adcq $0, %%rdx\n\t"
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"movq %%rax, %[lo3]\n\t"
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"movq %%rdx, %[hi0]\n\t"
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: [lo0]"=&r"(lo0), [lo1]"=&r"(lo1), [lo2]"=&r"(lo2), [lo3]"=&r"(lo3), [hi0]"=&r"(hi0)
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: [a0]"r"(a0), [b0]"m"(b->d[0]), [b1]"m"(b->d[1]), [b2]"m"(b->d[2]), [b3]"m"(b->d[3])
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: "rax", "rdx", "r8", "cc"
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);
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/* Row 1: accumulate a1 * b[0..3] into lo1..hi1 */
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__asm__ __volatile__(
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"movq %[a1], %%rax\n\t"
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"mulq %[b0]\n\t"
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"addq %%rax, %[lo1]\n\t"
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"adcq %%rdx, %[lo2]\n\t"
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"adcq $0, %[lo3]\n\t"
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"adcq $0, %[hi0]\n\t"
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"movq $0, %[hi1]\n\t"
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"adcq $0, %[hi1]\n\t"
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"movq %[a1], %%rax\n\t"
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"mulq %[b1]\n\t"
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"addq %%rax, %[lo2]\n\t"
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"adcq %%rdx, %[lo3]\n\t"
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"adcq $0, %[hi0]\n\t"
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"adcq $0, %[hi1]\n\t"
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"movq %[a1], %%rax\n\t"
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"mulq %[b2]\n\t"
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"addq %%rax, %[lo3]\n\t"
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"adcq %%rdx, %[hi0]\n\t"
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"adcq $0, %[hi1]\n\t"
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"movq %[a1], %%rax\n\t"
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"mulq %[b3]\n\t"
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"addq %%rax, %[hi0]\n\t"
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"adcq %%rdx, %[hi1]\n\t"
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: [lo1]"+r"(lo1), [lo2]"+r"(lo2), [lo3]"+r"(lo3), [hi0]"+r"(hi0), [hi1]"=&r"(hi1)
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: [a1]"r"(a1), [b0]"m"(b->d[0]), [b1]"m"(b->d[1]), [b2]"m"(b->d[2]), [b3]"m"(b->d[3])
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: "rax", "rdx", "cc"
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);
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/* Row 2: accumulate a2 * b[0..3] */
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__asm__ __volatile__(
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"movq %[a2], %%rax\n\t"
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"mulq %[b0]\n\t"
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"addq %%rax, %[lo2]\n\t"
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"adcq %%rdx, %[lo3]\n\t"
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"adcq $0, %[hi0]\n\t"
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"adcq $0, %[hi1]\n\t"
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"movq $0, %[hi2]\n\t"
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"adcq $0, %[hi2]\n\t"
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"movq %[a2], %%rax\n\t"
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"mulq %[b1]\n\t"
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"addq %%rax, %[lo3]\n\t"
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"adcq %%rdx, %[hi0]\n\t"
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"adcq $0, %[hi1]\n\t"
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"adcq $0, %[hi2]\n\t"
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"movq %[a2], %%rax\n\t"
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"mulq %[b2]\n\t"
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"addq %%rax, %[hi0]\n\t"
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"adcq %%rdx, %[hi1]\n\t"
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"adcq $0, %[hi2]\n\t"
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"movq %[a2], %%rax\n\t"
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"mulq %[b3]\n\t"
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"addq %%rax, %[hi1]\n\t"
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"adcq %%rdx, %[hi2]\n\t"
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: [lo2]"+r"(lo2), [lo3]"+r"(lo3), [hi0]"+r"(hi0), [hi1]"+r"(hi1), [hi2]"=&r"(hi2)
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: [a2]"r"(a2), [b0]"m"(b->d[0]), [b1]"m"(b->d[1]), [b2]"m"(b->d[2]), [b3]"m"(b->d[3])
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: "rax", "rdx", "cc"
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);
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/* Row 3: accumulate a3 * b[0..3] */
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__asm__ __volatile__(
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"movq %[a3], %%rax\n\t"
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"mulq %[b0]\n\t"
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"addq %%rax, %[lo3]\n\t"
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"adcq %%rdx, %[hi0]\n\t"
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"adcq $0, %[hi1]\n\t"
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"adcq $0, %[hi2]\n\t"
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"movq $0, %[hi3]\n\t"
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"adcq $0, %[hi3]\n\t"
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"movq %[a3], %%rax\n\t"
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"mulq %[b1]\n\t"
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"addq %%rax, %[hi0]\n\t"
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"adcq %%rdx, %[hi1]\n\t"
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"adcq $0, %[hi2]\n\t"
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"adcq $0, %[hi3]\n\t"
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"movq %[a3], %%rax\n\t"
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"mulq %[b2]\n\t"
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"addq %%rax, %[hi1]\n\t"
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"adcq %%rdx, %[hi2]\n\t"
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"adcq $0, %[hi3]\n\t"
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"movq %[a3], %%rax\n\t"
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"mulq %[b3]\n\t"
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"addq %%rax, %[hi2]\n\t"
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"adcq %%rdx, %[hi3]\n\t"
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: [lo3]"+r"(lo3), [hi0]"+r"(hi0), [hi1]"+r"(hi1), [hi2]"+r"(hi2), [hi3]"=&r"(hi3)
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: [a3]"r"(a3), [b0]"m"(b->d[0]), [b1]"m"(b->d[1]), [b2]"m"(b->d[2]), [b3]"m"(b->d[3])
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: "rax", "rdx", "cc"
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);
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/* Reduce: r = lo + hi * C using MULQ for hi[i]*C */
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uint64_t c = FIELD_C_ASM;
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__asm__ __volatile__(
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/* hi0 * C */
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"movq %[hi0], %%rax\n\t"
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"mulq %[c]\n\t"
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"addq %%rax, %[lo0]\n\t"
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"adcq %%rdx, %[lo1]\n\t"
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"adcq $0, %[lo2]\n\t"
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"adcq $0, %[lo3]\n\t"
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"sbbq %%r8, %%r8\n\t" /* r8 = -carry (0 or -1) */
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"negq %%r8\n\t" /* r8 = carry (0 or 1) */
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/* hi1 * C */
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"movq %[hi1], %%rax\n\t"
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"mulq %[c]\n\t"
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"addq %%rax, %[lo1]\n\t"
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"adcq %%rdx, %[lo2]\n\t"
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"adcq $0, %[lo3]\n\t"
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"adcq $0, %%r8\n\t"
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/* hi2 * C */
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"movq %[hi2], %%rax\n\t"
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"mulq %[c]\n\t"
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"addq %%rax, %[lo2]\n\t"
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"adcq %%rdx, %[lo3]\n\t"
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"adcq $0, %%r8\n\t"
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/* hi3 * C */
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"movq %[hi3], %%rax\n\t"
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"mulq %[c]\n\t"
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"addq %%rax, %[lo3]\n\t"
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"adcq %%rdx, %%r8\n\t"
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/* Final fold: r8 * C */
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"movq %%r8, %%rax\n\t"
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"mulq %[c]\n\t"
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"addq %%rax, %[lo0]\n\t"
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"adcq %%rdx, %[lo1]\n\t"
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"adcq $0, %[lo2]\n\t"
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"adcq $0, %[lo3]\n\t"
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: [lo0]"+r"(lo0), [lo1]"+r"(lo1), [lo2]"+r"(lo2), [lo3]"+r"(lo3)
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: [hi0]"r"(hi0), [hi1]"r"(hi1), [hi2]"r"(hi2), [hi3]"r"(hi3), [c]"r"(c)
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: "rax", "rdx", "r8", "cc"
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);
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r->d[0] = lo0; r->d[1] = lo1; r->d[2] = lo2; r->d[3] = lo3;
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fe_normalize(r);
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}
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#define FE_MUL_ASM 1
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#elif SECP_ARM64 && defined(__GNUC__)
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/*
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* ARM64 field multiply using MUL + UMULH pairs.
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* MUL gives the low 64 bits, UMULH gives the high 64 bits of a 64x64->128 product.
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* ADDS/ADCS chain for carry propagation.
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*/
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static inline void fe_mul_asm(secp256k1_fe *r, const secp256k1_fe *a, const secp256k1_fe *b) {
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uint64_t a0 = a->d[0], a1 = a->d[1], a2 = a->d[2], a3 = a->d[3];
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uint64_t b0 = b->d[0], b1 = b->d[1], b2 = b->d[2], b3 = b->d[3];
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uint64_t lo0, lo1, lo2, lo3, hi0, hi1, hi2, hi3;
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uint64_t tmp_lo, tmp_hi;
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/* Row 0: a0 * b[0..3] */
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__asm__ __volatile__(
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"mul %[lo0], %[a0], %[b0]\n\t"
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"umulh %[cy], %[a0], %[b0]\n\t"
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"mul %[tl], %[a0], %[b1]\n\t"
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"umulh %[th], %[a0], %[b1]\n\t"
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"adds %[lo1], %[tl], %[cy]\n\t"
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"adc %[cy], %[th], xzr\n\t"
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"mul %[tl], %[a0], %[b2]\n\t"
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"umulh %[th], %[a0], %[b2]\n\t"
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"adds %[lo2], %[tl], %[cy]\n\t"
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"adc %[cy], %[th], xzr\n\t"
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"mul %[tl], %[a0], %[b3]\n\t"
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"umulh %[hi0], %[a0], %[b3]\n\t"
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"adds %[lo3], %[tl], %[cy]\n\t"
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"adc %[hi0], %[hi0], xzr\n\t"
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: [lo0]"=&r"(lo0), [lo1]"=&r"(lo1), [lo2]"=&r"(lo2), [lo3]"=&r"(lo3),
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[hi0]"=&r"(hi0), [cy]"=&r"(tmp_hi), [tl]"=&r"(tmp_lo), [th]"=&r"(tmp_hi)
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: [a0]"r"(a0), [b0]"r"(b0), [b1]"r"(b1), [b2]"r"(b2), [b3]"r"(b3)
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: "cc"
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);
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/* Rows 1-3: use C with __int128 for clarity (ARM64 gcc handles this well) */
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/* The real win on ARM64 is in the reduction, not the product */
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{
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typedef unsigned __int128 u128;
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u128 acc;
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acc = (u128)lo1 + (u128)a1*b0;
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lo1 = (uint64_t)acc; acc >>= 64;
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acc += (u128)lo2 + (u128)a1*b1;
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lo2 = (uint64_t)acc; acc >>= 64;
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acc += (u128)lo3 + (u128)a1*b2;
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lo3 = (uint64_t)acc; acc >>= 64;
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acc += (u128)hi0 + (u128)a1*b3;
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hi0 = (uint64_t)acc; hi1 = (uint64_t)(acc>>64);
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acc = (u128)lo2 + (u128)a2*b0;
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lo2 = (uint64_t)acc; acc >>= 64;
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acc += (u128)lo3 + (u128)a2*b1;
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lo3 = (uint64_t)acc; acc >>= 64;
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acc += (u128)hi0 + (u128)a2*b2;
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hi0 = (uint64_t)acc; acc >>= 64;
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acc += (u128)hi1 + (u128)a2*b3;
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hi1 = (uint64_t)acc; hi2 = (uint64_t)(acc>>64);
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acc = (u128)lo3 + (u128)a3*b0;
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lo3 = (uint64_t)acc; acc >>= 64;
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acc += (u128)hi0 + (u128)a3*b1;
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hi0 = (uint64_t)acc; acc >>= 64;
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acc += (u128)hi1 + (u128)a3*b2;
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hi1 = (uint64_t)acc; acc >>= 64;
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acc += (u128)hi2 + (u128)a3*b3;
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hi2 = (uint64_t)acc; hi3 = (uint64_t)(acc>>64);
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/* Reduce: lo + hi * C */
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acc = (u128)lo0 + (u128)hi0 * FIELD_C_ASM;
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r->d[0] = (uint64_t)acc; acc >>= 64;
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acc += (u128)lo1 + (u128)hi1 * FIELD_C_ASM;
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r->d[1] = (uint64_t)acc; acc >>= 64;
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acc += (u128)lo2 + (u128)hi2 * FIELD_C_ASM;
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r->d[2] = (uint64_t)acc; acc >>= 64;
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acc += (u128)lo3 + (u128)hi3 * FIELD_C_ASM;
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r->d[3] = (uint64_t)acc;
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uint64_t carry = (uint64_t)(acc >> 64);
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if (carry) {
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acc = (u128)r->d[0] + (u128)carry * FIELD_C_ASM;
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r->d[0] = (uint64_t)acc; carry = (uint64_t)(acc >> 64);
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if (carry) { r->d[1] += carry; if (r->d[1] < carry) { r->d[2]++; if (!r->d[2]) r->d[3]++; } }
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}
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}
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fe_normalize(r);
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}
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#define FE_MUL_ASM 1
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#else
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#define FE_MUL_ASM 0
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#endif
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#endif /* SECP256K1_FIELD_ASM_H */
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